Makefile tips

Makefile working tips. Usual simple makefile looks like this:

make:
    gcc main.c -o main

but when your project grows and you use more files it becomes like this:

make:
    gcc -O2 -c file1.c
    gcc -O2 -c file2.c
    gcc -O2 -c file3.c
    gcc -O2 main.c file1.o file2.o file3.o -o main

This is standard growth of file. Its better practice to reuse your code, it could applied to your makefile also.

When you have few small project and you want simply copy makefile and it works.

Compiler name

Usually everyone prefer one compiler. And time to time only check if code compiles with other compilers.

CC=gcc
make:
    $(CC) -O2 -c file1.c
    $(CC) -O2 -c file2.c
    $(CC) -O2 -c file3.c
    $(CC) -O2 main.c file1.o file2.o file3.o -o main

Project name

Every project have unique name and you also would like to change it if there is need.

PROJECT=project
CC=gcc
make:
    $(CC) -O2 -c file1.c
    $(CC) -O2 -c file2.c
    $(CC) -O2 -c file3.c
    $(CC) -O2 main.c file1.o file2.o file3.o -o $(PROJECT)

Compiler flags

Usual problem is when some compiling flags causes problems and you need to change every single entry in file.

PROJECT=project
CC=gcc
CFLAGS=-O2
make:
    $(CC) $(CFLAGS) -c file1.c
    $(CC) $(CFLAGS) -c file2.c
    $(CC) $(CFLAGS) -c file3.c
    $(CC) $(CFLAGS) main.c file1.o file2.o file3.o -o $(PROJECT)

This 3 variables reduce how number of places that you need to edit if something changes.

Next thing is to fix problem when you need to add or remove file from project and after that you have manually to edit at least 2 lined in makefile.

Use multiple files

One of they ways how to reduce number of files edited is to add new variable where all files is listed:

PROJECT=project
CC=gcc
CFLAGS=-O2
SOURCES=file1.c file2.c file3.c
OBJECTS=$(SOURCES:.c=.o)

all: $(OBJECTS) $(PROJECT)

$(PROJECT): $(SOURCES) main.c
    $(CC) $(OBJECTS) $(CFLAGS) main.c -o $(PROJECT)

%.o: %.c
    $(CC) $(CFLAGS) -c $<

Here was added file auto-matching for .c files to make them .o

Auto matching C files

Last thing to add is auto match all *.c in directory.

PROJECT=project
CC=gcc
CFLAGS=-O2
SOURCES=$(wildcard *.c)
OBJECTS=$(SOURCES:.c=.o)

all: $(OBJECTS) $(PROJECT)

$(PROJECT): $(SOURCES) main.c
    $(CC) $(OBJECTS) $(CFLAGS) -o $(PROJECT)

%.o: %.c
    $(CC) $(CFLAGS) -c $<

Now project makefile can be easily copied and with changing only one variable value everything should be OK To run any makefile:

make -f makefile_name.mk

Downloads

makefile_tips.zip 3KiB - http://archive.main.lv/files/writeup/makefile_tips/makefile_tips.zip